Events in SV and UVM

In this blog, we will see the details of UVM functions use for uvm_event and it can be used in place of SV (system verilog) event.

In system verilog, event data type is used for synchronization of different processes and similar concept is there in UVM which have “uvm_event” class. Here, we will see the similarities between them.

Below is the example code for usage of sv event (Figure 1) and uvm event (Figure 2). Output is shown just below the figure.

In the example, two events (e1_* and e2_*) are used. Both events are triggered followed by waiting on the same event. But due to, "@" operator and "wait_trigger()" method, it doesn't get the event triggered and it waits for the event e1_* to be triggered. In case of, e2_* event, "wait(event.triggered)" and "wait_ptrigger()" method is used which allows process to be unblocked as event is triggered in the same simulation time. From output, the same behavior can be observed.

OUTPUT:

#  e2_sv is triggered at                   20

#  e2_uvm is triggered at                20

#  e2_sv is triggered at                   40

#  e2_uvm is triggered at                40

#  e2_sv is triggered at                   60

#  e2_uvm is triggered at                60

SV & UVM events comparison:

Event Triggering:

In SV, events can be triggered via the “-> event” operator which unblock all processes currently waiting on that event.

In UVM, "event.trigger()" method is used to trigger the event to unblock the processes.

Waiting for event:

In SV, "@(event)" operator is used to wait for an event to be triggered.

In UVM, "event.wait_trigger()" method is used to wait for an event to be triggered.

Persistent trigger:

In SV, "wait (event.triggered)" will unblock the waiting process whether the wait executes before or at the same  simulation time as the trigger operation.

In UVM, "event.wait_ptrigger()" method will unblock the waiting process at same simulation time as the trigger operation.