How to find UVM port connections between components in the testbench?

UVM provides ports for communicating between components. So that, we can easily transfer packets from one component to another component in blocking/non-blocking mode. These ports can be connected to any components in the testbench based on the requirements. In env, we connect these ports with respective port/export/implementation port to get packets. Occasionally, we come across a situation when a driver put the packet in the port but the packet is not received in the respective component.

Here, first question comes to our mind is, whether the ports are connected properly or not. For that, UVM has provided “debug_connected_to” and “debug_provided_to” methods which gives a print of procedural connected components  through TLM which make debugging task easier. So, if the components are not connected properly then we can update the port connection to resolve the problem.

“debug_connected_to” method gives display of the implementation/export to which this port is connected i.e. port is driving packets to which port/export/imp. “debug_provided_to” methods gives display of the port/export to which this imp/export is connected i.e. imp/export is getting data from which port/export.

Below is an example of port-export connection which is similar to the example given in UVM 1.2 Class Reference (Topic 14. TLM1 Interfaces, Ports, Exports and Transport Interfaces).

Figure 1 

Here, comp1, subcomp1 and leaf1 components are connected via port and leaf1 component put the packets on the port. Components comp2, subcomp2 and leaf2 components are connected through export and in leaf2 component contains implementation put method. Components comp1 and comp2 are connected through port-export connection.

• Output of “out.debug_connected_to()” of “comp1”:

It describes the export-imp connection chain of all components with full hierarchy details and port type i.e. where the put method is implemented.

# UVM_INFO @ 0: env.comp1.out [debug_connected_to] This port's fanout network:

#   env.comp1.out (uvm_blocking_put_port)

#     |

#     |_env.comp2.in (uvm_blocking_put_export)

#         |

#         |_env.comp2.subcomp2.in (uvm_blocking_put_export)

#             |

#             |_env.comp2.subcomp2.leaf2.in (uvm_blocking_put_imp)

#   Resolved implementation list:

#   0: env.comp2.subcomp2.leaf2.in (uvm_blocking_put_imp)

As shown above, comp1’s put port (out) is connected with comp2’s put export (in) which is connected with subcomp2’s put export (in) and its implementation method is n leaf2 component which has put imp (in). 

• Output of "out.debug_provided_to()" of "comp1":

It describes the port connection chain of all components with full hierarchy details and port type i.e. from where the component put the packet on the port.

# UVM_INFO @ 0: env.comp1.out [debug_provided_to] This port's fanin network:

#   env.comp1.out (uvm_blocking_put_port)

#     |

#     |_env.comp1.subcomp1.out (uvm_blocking_put_port)

#         |

#         |_env.comp1.subcomp1.leaf1.out (uvm_blocking_put_port)

As shown above, comp1’s out port is connected with subcomp1’s out port which is connected with leaf1’s out port. Here, leaf1 component drives packets on the port. So, up to “leaf1.out” port hierarchy is printed in the output.

Similarly, we can get information for any port/export. Below is the output for “in” export of comp2 component.

• Output of “in.debug_connected_to()” of “comp2”:

             # UVM_INFO @ 0: env.comp2.in [debug_connected_to] This port's fanout network:

             #   env.comp2.in (uvm_blocking_put_export)

             #     |

             #     |_env.comp2.subcomp2.in (uvm_blocking_put_export)

             #         |

             #         |_env.comp2.subcomp2.leaf2.in (uvm_blocking_put_imp)

             #

             #   Resolved implementation list:

             #   0: env.comp2.subcomp2.leaf2.in (uvm_blocking_put_imp)

• Output of “in.debug_provided_to()” of “comp2”:

             # UVM_INFO @ 0: env.comp2.in [debug_provided_to] This port's fanin network:

             #   env.comp2.in (uvm_blocking_put_export)

             #     |

             #     |_env.comp1.out (uvm_blocking_put_port)

             #         |

             #         |_env.comp1.subcomp1.out (uvm_blocking_put_port)

             #             |

             #             |_env.comp1.subcomp1.leaf1.out (uvm_blocking_put_port)