System Verilog Polymorphism

                  

As a fresher coming from Electronics & Communication branch, it was very difficult for me to work directly on System Verilog especially, I don’t know OOPs concepts. Encapsulation, Inheritance and Polymorphism are the most commonly used in System Verilog.

Polymorphism allows the use of a variable of the superclass type to hold subclass objects and to reference the methods of those subclasses directly from the superclass variable. So, you can say Polymorphism = Virtual Methods + Inheritance.

Virtual method overrides in subclasses shall have matching argument types, identical argument names, identical qualifiers, and identical directions to the prototype.

The virtual qualifier is optional in the derived class method declarations. So, if any method declared as virtual in the base class then by default same method works as virtual in child class.

In below example, Animal is a top class, Dog class is derived from Animal class and Puppy class is derived from Dog class. In Animal class which is a base class, eat() method is declared as a virtual method. In derived class Dog, same method is implemented but it is not declared as virtual.

Example:

module top;

   class Animal;

       virtual function eat();

         $display("Animal eat");

       endfunction

   endclass

 

  class Dog extends Animal;

       function eat();

         $display("Dog eat");

       endfunction

  endclass

  class Puppy extends Dog;

       function eat();

         $display("Puppy eat");

       endfunction

  endclass

  initial begin

  Animal a_handle;

  Dog d_handle;

  Puppy p_handle;

  a_handle = new();

  d_handle= new();

  p_handle= new();

  a_handle.eat(); 

  d_handle.eat(); 

  p_handle.eat(); 

  a_handle = d_handle;

  a_handle.eat(); 

  d_handle.eat(); 

  p_handle.eat(); 

  a_handle = p_handle;

  a_handle.eat(); 

  d_handle.eat(); 

  p_handle.eat(); 

  d_handle = p_handle;

  a_handle.eat(); 

  d_handle.eat(); 

  p_handle.eat(); 

end

endmodule

Output:

Animal eat 
Dog eat
Puppy eat  

Dog eat
Dog eat
Puppy eat
 
Puppy eat
Dog eat
Puppy eat

Puppy eat  
Puppy eat 
Puppy eat  
 

As shown above, while calling eat() method of Animal, Dog and Puppy class, respective method is called from respective class. But when handle of Dog class instance is passed to Animal class instance then eat() method of Dog class is called while calling eat() method of Animal class(a_handle.eat()).

Same way, after assigning handle of Puppy class to instance of Animal class, eat() method of Puppy class is called while calling eat() method of Animal class (a_handle.eat()).

Now, if handle of Puppy class is assigned to Dog class instance then eat() method of Puppy class is called every time when eat() method of any class (Animal or Dog or Puppy) is called. Here, while calling eat() method of Animal class, eat() method of Puppy class is called. The reason behind it is, previously, p_handle is assigned with the a_handle.

As shown in the above example, eat() method is not virtual in Dog class but it works as virtual because same method is defined as virtual in it’s parent class.

Reference:
(1) IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language,IEEE Std 1800™-2012